The present invention relates to a semiconductor integrated circuit having an instruction register.
Since a RAM and a ROM for a number of data are required in general in digital signal processing and an pointer control is frequently necessary at every data calculation, an instruction format is composed to simultaneously calculate for accelerating a process and to control the pointer in a digital signal processor. The pointer means an addressing register for a RAM or a ROM.
FIG. 3 is a block diagram showing a conventional digital signal processor. Referring to FIG. 3, the conventional digital signal processor includes a 512-words 23 bits instruction ROM 1, a 23-bit length instruction register 2, a pointer control circuit 5, a 7-bit length data pointer (hereinafter referred to as "DP") 6, a data RAM 7, a 9-bit length ROM pointer (hereinafter referred to as "RP") 9, and a data ROM 10.
This processor inputs an instruction read from the instruction ROM 1 in the instruction register 2, and uses specific fields of the instruction register 2 to control the two pointers, i.e., the DP 6 and the RP 9.
FIG. 4 is a view showing an operation instruction format 20b of one of four instruction formats of the processor in FIG. 3.
The operation instruction format 20b can control the two pointers, and has eight fields. When a field 21 having 22nd bit and 21st bit is "00", it indicates an operation instruction. A P-SEL field 22 having 20th and 19th bits selects a P input of an arithmetic and logic unit (hereinafter referred to as "an ALU"), an ALU field 23 having 18th to 15th bits assigns the function of the ALU, an ASL field 24 having 14th bit assigns to select an accumulator A or B for the input/output of the ALU, and these three fields mainly assigns the control of ALU execution. A DP.sub.L field 25 having 13th and 12th bits alters the values of less significant 4 bits of the DP 6, a DP.sub.H.M field 25 having 11th to 9th bits modifies or alters the more significant 3 bits of the data pointer, an RPDCR field 27 having 8th bit assigns to decrement (-1) the content of the RP or not, and these three fields mainly assign the control of the pointers. An SRC field 28 having 7th to 4th bits assigns a register which outputs the content to an internal data bus, a DST field 29 having 3rd to 0th bits assigns a register which inputs the content of the internal data bus, and these two fields mainly assign the control of the internal but transfer.
In the processor in FIG. 3, the two pointers are controlled by 6 bits of 3th to 8th bits simultaneously upon assigning of calculation of the ALU.
field for controlling the pointers are operated as below.
The DP 6 is controlled by 5 bits of the DP.sub.L field 5 and the DP.sub.H.M field 26. The DP.sub.L field 25 can assign the 4 kinds of function to control the less significant 4 bits of the DP 6 for NOP (no-operation), increment (+1), decrement (-1) and zero clear. An exclusive OR (XOR) is calculated with the values of the 3 bits of the DP.sub.H.M field 26 and the values of the more significant 3 bits of the DP 6, and the result is returned to the more significant 3 bits of the DP 6. If the more significant 3 bits are not desired to be altered, the DP.sub.H.M field 26 may be set to "000". If only the most significant bit is desired to be inverted, the field 26 may be set to "100". This is mainly used for assigning the page of the data RAM 7. The RP 9 is controlled only by 1 bit of the RPDCR field 27. The content is mere decrement as described above to have low degree of freedoms as compared with the DP 6. For example, to alter the assignment of the page of the data ROM 10, the following three step processes are necessarily executed.
(1) A bit pattern to be used for the XOR calculation is loaded (stored) in the accumulator A. PA1 (2) The value of the RP 9 is calculated through the internal bus by the ALU for the XOR. PA1 (3) The result stored in the accumulator A is again returned to the RP 9.
Thus, in the prior art, to obtain the same degree of freedoms of the control as the DP 6 for the RP 9, the RP 9 must be controlled in the 5 bit length instruction field, and the instruction register 2 is lengthened for another 4 bit length.
When the number of the pointers is increased or the degree of freedoms of addressing is raised in the above-mentioned conventional semiconductor integrated circuit, the number of fields is increased, and the bit length of the instruction register is increased. Thus, there arise drawbacks that the memory capacity of the program is increased, and wasteful fields exist when the pointer and the calculation are not simultaneously assigned. Therefore, to suppress the price of the integrated circuit, the control of the pointers is limited in tee conventional processor. Thus, the conventional processor has such drawbacks that the number of steps of the program is increased and the executing speed is decelerated.